vibefab

The whole chip stack, from a sentence — Verilog synthesized to a gate schematic, placed as standard cells (GDS), and fabricated in 3D by a real plasma-etch solver. Full-stack builds, logic, and fab runs below.

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full stack

full_adder

Verilog → schematic → layout → 3D fab · tabbed
veriloggds3d
gates 5 cells 53.3×1.0 µm²
logic

counter2

synthesized gate schematic
verilogyosys
gates 4 depth 12/2 i/o
logic

full_adder

synthesized gate schematic
verilogyosys
gates 7 depth 43/2 i/o
logic

mux4

synthesized gate schematic
verilogyosys
gates 3 depth 26/1 i/o

copper-damascene

0. substrate
1. mask (trench)
2. etch to 0.35µm
3. strip
4. deposit liner 0.03µm
5. deposit copper 0.21µm
6. CMP planarize
siliconlinercopper
dx 20nm14 frames sim 8.78s

deep-via

0. substrate
1. mask (via)
2. etch to 0.8µm
3. wet etch 0.04µm
4. deposit film 0.05µm
5. strip
siliconfilm
dx 20nm14 frames sim 25.7s

gds-layer1

0. substrate
1. mask (gds L1)
2. etch to 0.45µm
3. strip
silicon
dx 25nm7 frames sim 11.09s

l-and-pads

0. substrate
1. mask (3 polygons)
2. etch to 0.5µm
3. deposit film 0.05µm
4. strip
siliconfilm
dx 25nm11 frames sim 14.04s

m1-v1-stack

0. substrate
1. mask (gds L1)
2. etch to 0.25µm
3. strip
4. deposit liner 0.03µm
5. deposit copper 0.16µm
6. CMP planarize
7. deposit oxide 0.2µm
8. mask (gds L2)
9. etch to 0.04µm
10. strip
11. deposit tungsten 0.15µm
12. CMP planarize
siliconlinercopperoxidetungsten
dx 25nm24 frames sim 14.98s

trench-liner

0. substrate
1. mask (trench)
2. etch to 0.7µm
3. deposit film 0.06µm
4. strip
siliconfilm
dx 20nm12 frames sim 21.03s