vibefab / design

module counter2 · synthesized gate schematic
4
gates
1
logic depth
2/2
in / out
clk rst q[0] q[1]
verilog source
module counter2(input clk, input rst, output [1:0] q);
  reg [1:0] q;
  always @(posedge clk) q <= rst ? 2'b0 : q + 1;
endmodule