vibefab / design

module full_adder · synthesized gate schematic
7
gates
4
logic depth
3/2
in / out
a b cin sum cout
verilog source
module full_adder (
    input  a,
    input  b,
    input  cin,
    output sum,
    output cout
);
    assign sum  = a ^ b ^ cin;
    assign cout = (a & b) | (b & cin) | (a & cin);
endmodule