vibefab / design

module mux4 · synthesized gate schematic
3
gates
2
logic depth
6/1
in / out
d[0] d[1] d[2] d[3] s[0] s[1] y
verilog source
module mux4(input [3:0] d, input [1:0] s, output y);
  assign y = d[s];
endmodule